Software pipelining: An effective scheduling technique for VLIW machines

DMCA

Software pipelining: An effective scheduling technique for VLIW machines (1988)

Cached

Download Links

Other Repositories/Bibliography

DBLP

by Monica Lam

Citations:

578 - 3 self

BibTeX

@INPROCEEDINGS{Lam88softwarepipelining:,
    author = {Monica Lam},
    title = {Software pipelining: An effective scheduling technique for VLIW machines},
    booktitle = {},
    year = {1988},
    pages = {318--328}
}

OpenURL

Abstract

This paper shows that software pipelining is an effective and viable scheduling technique for VLIW processors. In software pipelining, iterations of a loop in the source program are continuously initiated at constant intervals, before the preceding iterations complete. The advantage of software pipelining is that optimal performance can be achieved with compact object code. This paper extends previous results of software pipelining in two ways: First, this paper shows that by using an im-proved algorithm, near-optimal performance can be obtained without specialized hardware. Second, we propose a hierarchical reduction scheme whereby entire control con-structs are reduced to an object similar to an operation in a basic block. With this scheme, all innermost loops, including those containing conditional statements, can be software pipelined. It also diminishes the start-up cost of loops with small number of iterations. Hierarchical reduction comple-ments the software pipelining technique, permitting a consis-tent performance improvement be obtained. The techniques proposed have been validated by an im-plementation of a compiler for Warp, a systolic array consist-ing of 10 VLIW processors. This compiler has been used for developing a large number of applications in the areas of image, signal and scientific processing.

Keyphrases

software pipelining effective scheduling technique vliw machine vliw processor hierarchical reduction scheme large number source program previous result entire control con-structs preceding iteration innermost loop systolic array consist-ing basic block im-proved algorithm constant interval hierarchical reduction comple-ments specialized hardware consis-tent performance improvement conditional statement start-up cost scientific processing optimal performance small number compact object code viable scheduling technique near-optimal performance

DMCA