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64-bit and Multimedia Extensions for the PA-RISC 2.0 Architecture (1996)
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| Venue: | Proceedings of IEEE Compcon, February |
| Citations: | 8 - 2 self |
BibTeX
@INPROCEEDINGS{Lee9664-bitand,
author = {Ruby Lee and Jerry Huck},
title = {64-bit and Multimedia Extensions for the PA-RISC 2.0 Architecture},
booktitle = {Proceedings of IEEE Compcon, February},
year = {1996},
pages = {152--160},
publisher = {IEEE CS Press}
}
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Abstract
This paper describes the architectural extensions to the PA-RISC 1.1 architecture to enable 64-bit processing of integers and pointers. It also describes MAX, the Multimedia Acceleration eXtensions which speed up the processing of multimedia and other applications with parallelism at the intra instruction, or subword, level. Other additions to the PA-RISC 2.0 architecture include performance enhancements with respect to memory hierarchy management, branch penalty reduction, and floating-point performance. 1. PA-RISC architecture evolution When the original PA-RISC 1.0 Architecture was designed in the early eighties, its goal was to be a single architecture that efficiently spans Hewlett-Packard's three computer lines: the HP3000 commercial minicomputers, the HP9000 technical workstations and servers, and the HP1000 realtime controllers. Before introduction, the program was codenamed SPECTRUM. At introduction in 1986, it was known as HP's Precision Architecture [1,2], HP-PA, or just PA. Subsequently, the architecture was called PA-RISC, with the first version of the architecture known as PA-RISC 1.0. Since its introduction, the PA-RISC architecture has remained remarkably stable. Only minor changes were made over the next decade, to facilitate higher performance in floating-point and system processing. When PA-RISC 1.0 was designed, floating-point performance was not essential for the majority of the HP computer systems targeted at that time. Hence, the architecture defined floating-point support as optional coprocessor instructions, without emphasizing high performance. In 1989, driven by the performance needs of the HP9000 technical workstation line, PA-RISC 1.1 was introduced. This included additional floating-point capabilities, such as more floating-point registers, doubling the amount of register space for single-precision floating-point numbers, and introducing combined operation floating-point
Keyphrases
multimedia extension floating-point performance additional floating-point capability performance need hp3000 commercial minicomputer floating-point support single-precision floating-point number hp computer system hp9000 technical workstation early eighty computer line architectural extension multimedia acceleration extension hp1000 realtime controller single architecture high performance intra instruction combined operation floating-point minor change 64-bit processing next decade original pa-risc first version branch penalty reduction pa-risc architecture evolution optional coprocessor instruction system processing hierarchy management precision architecture performance enhancement register space floating-point register pa-risc architecture hp9000 technical workstation line
