Using a User-Level Memory Thread for Correlation Prefetching

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Using a User-Level Memory Thread for Correlation Prefetching (2002)

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by Yan Solihin , Jaejin Lee , Josep Torrellas

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79 - 4 self

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@MISC{Solihin02usinga,
    author = {Yan Solihin and Jaejin Lee and Josep Torrellas},
    title = {Using a User-Level Memory Thread for Correlation Prefetching},
    year = {2002}
}

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Abstract

This paper introduces the idea of using a User-Level Memory Thread (ULMT) for correlation prefetching. In this approach, a user thread runs on a general-purpose processor in main memory, either in the memory controller chip or in a DRAM chip. The thread performs correlation prefetching in software, sending the prefetched data into the L2 cache of the main processor. This approach requires minimal hardware beyond the memory processor: the correlation table is a software data structure that resides in main memory, while the main processor only needs a few modifications to its L2 cache so that it can accept incoming prefetches. In addition, the approach has wide usability, as it can effectively prefetch even for irregular applications. Finally, it is very flexible, as the prefetching algorithm can be customized by the user on an application basis. Our simulation results show that, through a new design of the correlation table and prefetching algorithm, our scheme delivers good results. Specifically, nine mostly-irregular applications show an average speedup of 1.32. Furthermore, our scheme works well in combination with a conventional processor-side sequential prefetcher, in which case the average speedup increases to 1.46. Finally, by exploiting the customization of the prefetching algorithm, we increase the average speedup to 1.53.

Keyphrases

correlation prefetching user-level memory thread average speedup main memory l2 cache main processor correlation table application basis minimal hardware prefetching algorithm user thread scheme delivers good result memory processor new design software data structure general-purpose processor incoming prefetches simulation result memory controller chip irregular application conventional processor-side sequential prefetcher wide usability mostly-irregular application dram chip

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