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Cache Design for Embedded Real-Time Systems (1999)
| Venue: | Proceedings of the Embedded Systems Conference, Summer |
| Citations: | 9 - 0 self |
BibTeX
@INPROCEEDINGS{Jacob99cachedesign,
author = {Bruce Jacob},
title = {Cache Design for Embedded Real-Time Systems},
booktitle = {Proceedings of the Embedded Systems Conference, Summer},
year = {1999}
}
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Abstract
Caches have long been a mechanism for speeding memory access and are popular in embedded hardware architectures from microcontrollers to core-based ASIC designs. However, caches are considered ill-suited for embedded real-time systems because they provide a probabilistic performance boost— a cache may or may not contain the desired data at any given moment. Analysis that guarantees when an item will or will not be in the cache has proven difficult, so many real-time systems simply disable caching and schedule tasks based on worst-case memory access time. Yet there are several cache organizations that provide the benefit of caching without the real-time drawbacks of hardware-managed caches. These are software-managed caches, and several different examples can be found, from DSP-style on-chip RAM to academic designs. This paper compares the operation and organization of caches as found in general-purpose processors, microcontrollers, and DSPs; it also discusses designs for embedded realtime systems. 1
Keyphrases
embedded real-time system cache design general-purpose processor real-time drawback hardware-managed cache several different example worst-case memory access time embedded realtime system several cache organization memory access probabilistic performance core-based asic design embedded hardware architecture schedule task software-managed cache disable caching many real-time system dsp-style on-chip ram
