On Whitespace and Stability in Physical Synthesis

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On Whitespace and Stability in Physical Synthesis

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by Saurabh N. Adya , Igor L. Markov , Paul G. Villarrubia

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@MISC{Adya_onwhitespace,
    author = {Saurabh N. Adya and Igor L. Markov and Paul G. Villarrubia},
    title = {On Whitespace and Stability in Physical Synthesis},
    year = {}
}

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Abstract

In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible gate sizing, net buffering and detail placement require a certain amount of unused space in every region of the die. The need for “local” whitespace is further emphasized by temperature and power-density limits as well as the increasing use of buffered interconnect. Another requirement, the stability of placement results from run to run, is important to the convergence of physical synthesis loops. Indeed, logic re-synthesis targeting local congestion in a given placement or particular critical paths may be irrelevant for another placement pro-duced by the same or a different layout tool. In this work we offer solutions to the above problems. We show how to tie the results of a placer to a previously exist-ing placement, and yet leave room for optimization. In our experiments this technique produces placements with similar congestion maps. We also show how to trade off wirelength for routability by manipulating whitespace. Empirically, our techniques improve circuit delay of sparse layouts in conjunction with physical synthesis. Our proposed techniques can be implemented using existing commercial placement tools without source code modifications and with modest over-head. They can also be integrated directly into min-cut placers with negligible overhead. We consider in particular detail the problem of scaling existing IP blocks to increase their porosity. Indeed, the need for additional repeater insertion when migrating a block to a newer process node often implies re-optimizing the layout. Our techniques for achieving placement stability allow one to rescale an existing layout with different minimum local whitespace requirements. In contrast to current ECO techniques, our rescaling method is not restricted to small changes of the netlist and layout, but will attempt to keep the relative placements similar if that is possible.

Keyphrases

physical synthesis similar congestion map flexible gate sizing placement result incremental change commercial placement tool source code modification current eco technique negligible overhead physical synthesis loop local whitespace net buffering relative placement local congestion exist-ing placement small change buffered interconnect ip block different layout tool power-density limit particular critical path detail placement additional repeater insertion different minimum local whitespace requirement large-scale standard-cell placement algorithm particular detail min-cut placer certain amount circuit delay placement stability unused space logic re-synthesis sparse layout

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