Exploiting parallelism and structure to accelerate the simulation of chip multi-processors

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Exploiting parallelism and structure to accelerate the simulation of chip multi-processors (2006)

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by David A. Penry , Daniel Fay , David Hodgdon , Ryan Wells , Graham Schelle , David I. August , Dan Connors

Venue:	in Proc. of the Twelfth Int. Symp. on High-Performance Computer Architecture
Citations:	41 - 6 self

BibTeX

@INPROCEEDINGS{Penry06exploitingparallelism,
    author = {David A. Penry and Daniel Fay and David Hodgdon and Ryan Wells and Graham Schelle and David I. August and Dan Connors},
    title = {Exploiting parallelism and structure to accelerate the simulation of chip multi-processors},
    booktitle = {in Proc. of the Twelfth Int. Symp. on High-Performance Computer Architecture},
    year = {2006},
    pages = {29--40}
}

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Abstract

Simulation is an important means of evaluating new microarchitectures. Current trends toward chip multiprocessors (CMPs) try the ability of designers to develop efficient simulators. CMP simulation speed can be improved by exploiting parallelism in the CMP simulation model. This may be done by either running the simulation on multiple processors or by integrating multiple processors into the simulation to replace simulated processors. Doing so usually requires tedious manual parallelization or re-design to encapsulate processors. Both problems can be avoided by generating the simulator from a concurrent, structural model of the CMP. Such a model not only resembles hardware, making it easy to understand and use, but also provides sufficient information to automatically parallelize the simulator without requiring manual model changes. Furthermore, individual components of the model such as processors may be replaced with equivalent hardware without requiring repartitioning. This paper presents techniques to perform automated simulator parallelization and hardware integration for CMP structural models. We show that automated parallelization can achieve an 7.60 speedup for a 16-processor CMP model on a conventional 4-processor shared-memory multiprocessor. We demonstrate the power of hardware integration by integrating eight hardware PowerPC cores into a CMP model, achieving a speedup of up to 5.82. 1.

Keyphrases

chip multi-processors hardware integration multiple processor tedious manual parallelization efficient simulator automated parallelization 16-processor cmp model cmp simulation speed chip multiprocessor new microarchitectures sufficient information individual component structural model automated simulator parallelization hardware powerpc conventional 4-processor shared-memory multiprocessor important mean simulated processor equivalent hardware manual model change cmp structural model cmp simulation model cmp model

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