FPGA-based high-order finite difference algorithm for 2D acoustic wave propagation problems

FPGA-based high-order finite difference algorithm for 2D acoustic wave propagation problems (2005)

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by Chuan He , Wei Zhao , Mi Lu

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@MISC{He05fpga-basedhigh-order,
    author = {Chuan He and Wei Zhao and Mi Lu},
    title = {FPGA-based high-order finite difference algorithm for 2D acoustic wave propagation problems},
    year = {2005}
}

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Abstract

Finite Difference Time Domain (FDTD) method is the most commonly used numerical algorithm for simulating linear wave propagation phenomena in geophysics, electromagnetics, and aero- or marineacoustics applications. Unfortunately, evaluating timeevolution for millions to trillions of discrete spatial points is computational intensive, especially when the geometrical size under study is much larger than the wavelength of excitations or long time integration is needed. In this paper, we proposed an FPGA-based hardware implementation to accelerate these simulation tasks. By adopting high-order temporal and spatial finite difference numerical algorithms along with efficient on-chip memory architecture, we alleviate the bandwidth bottleneck between the FPGA chip and onboard memories at the cost of increased computational burdens, which are absorbed effectively into the pipelined computing engine without speed penalty. The speed of our design implemented on Xilinx ML401 Virtex-4 evaluation platform is about 7~20 times faster than a pure software implementation of the same algorithm running on a 3.0GHz DELL workstation. Moreover, the desirable properties of simplicity and scalability make our design compatible with most commercial reconfigurable coprocessor platforms and correspondingly, the performance would be proportional to their available onboard memory bandwidth. 1. Motivation and

Keyphrases

acoustic wave propagation problem fpga-based high-order finite difference algorithm simulation task fpga-based hardware implementation desirable property linear wave propagation phenomenon speed penalty spatial finite difference numerical algorithm efficient on-chip memory architecture marineacoustics application long time integration onboard memory dell workstation fpga chip xilinx ml401 virtex-4 evaluation platform available onboard memory bandwidth increased computational burden pure software implementation geometrical size used numerical algorithm commercial reconfigurable coprocessor platform bandwidth bottleneck discrete spatial point finite difference time domain