Abstract

Abstract — With the advent of 3D chip stacking technology, application-specific and heterogeneous three dimensional chip multi-processors (3D CMPs) are projected to become the building blocks of future parallel processing systems. In such 3D CMPs, network-on-chip (NoC) architectures will enable communication between multiple heterogeneous cores. However, NoCs face several challenges, including limited bandwidth, high latency, and high power dissipation. Hybrid nanophotonic-electric NoCs are being considered as a solution to address the above challenges due to their desirable performance and power characteristics. These emerging communication architectures require substantial optimization to realize their full potential. Optimizing hybrid nanophotonic-electric 3D NoCs requires intelligent traversal through a massive design space, which is non-trivial. No prior work has addressed the problem of synthesizing and optimizing application-specific hybrid nanophotonic-electric 3D NoCs with an irregular topology to connect heterogeneous cores on a 3D CMP. Considering the above unaddressed major challenge, in this paper we propose a synthesis framework called 3D-HELIX that can optimize application-specific hybrid nanophotonic-electric 3D NoCs. Our target communication fabric combines electrical 3D NoCs with an irregular topology and a single layer of free-space nanophotonics. Based on our experimental studies, we demonstrate that 3D-HELIX can produce superior NoC architectures achieving up to 6 × power savings while meeting application performance constraints, compared to 3D electrical NoC-based communication fabrics. 1.