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Efficient congestion-oriented custom Network-on-Chip topology synthesis (2010)
| Venue: | IEEE Int. Conf. on Reconfigurable Computing and FPGAs (ReConFig |
| Citations: | 1 - 1 self |
BibTeX
@INPROCEEDINGS{Ababei10efficientcongestion-oriented,
author = {Cristinel Ababei},
title = {Efficient congestion-oriented custom Network-on-Chip topology synthesis},
booktitle = {IEEE Int. Conf. on Reconfigurable Computing and FPGAs (ReConFig},
year = {2010}
}
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Abstract
Abstract—We propose a new custom Network-on-Chip (NoC) topology synthesis methodology consisting of floorplan-ning, routers assignment, and routing paths calculation steps. The proposed heuristic methodology integrates fast algorithms based on the B*-tree representation for floorplanning, on bipartite matching for the routers assignment step, and on multicommodity flow for congestion minimization for the rout-ing paths calculation step. Hence, it is able to explore a large portion of the solution space efficiently. Network performance is estimated using an integrated cycle-accurate simulator. Experimental results demonstrate that custom irregular NoC topologies can achieve latencies comparable to those achieved by 2-layer 3D regular mesh topologies. The multicommodity flow based routing paths calculation is proven to be effective in improving the average latency at high packet injection rates. Keywords-irregular Network-on-Chip; topology synthesis; multicommodity flow; I.
