BibTeX
@MISC{Jacobson_designand,
author = {Hans Jacobson},
title = {Design and Validation of a Simultaneous Multi-Threaded DLX Processor},
year = {}
}
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Abstract
Abstract | Modern day computer systems rely on two forms of parallelism to achieve high performance, parallelism between individual instructions of a program (ILP) and par-allelism between individual threads (TLP). Superscalar pro-cessors exploit ILP by issuing several instructions per clock, and multiprocessors (MP) exploit TLP by running dierent threads in parallel on dierent processors. A fundamental limitation of these approaches to exploit parallelism is that processor resources are statically parti-tioned. If TLP is low, processors in a MP system will be idle, and if ILP is low, issue slots in a superscalar processor will be wasted. As a consequence, the hardware cannot adapt to changing levels of ILP and TLP and resource utilization tend to be low. Since resource utilization is low there is potential to achieve higher performance if somehow useful instructions could be found to ll up the wasted issue slots. This pa-per explores a method called simultaneous multithreading (SMT) that addresses the utilization problem by letting multiple threads compete for the resources of a single pro-cessor each clock cycle thus increasing the potential ILP available. I.
Keyphrases
simultaneous multi-threaded dlx processor superscalar pro-cessors exploit ilp multiple thread abstract modern day computer system utilization problem potential ilp processor resource hardware cannot adapt single pro-cessor dierent processor high performance superscalar processor fundamental limitation dierent thread simultaneous multithreading utilization tend mp system issue slot clock cycle wasted issue slot individual instruction several instruction individual thread useful instruction resource utilization
