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Mechanisms and Evaluation of Cross-Layer Fault-Tolerance for Supercomputing
| Citations: | 1 - 0 self |
BibTeX
@MISC{Ho_mechanismsand,
author = {Chen-han Ho and Marc Kruijf and Karthikeyan Sankaralingam and Barry Rountree and Martin Schulz and Bronis R. Supinski},
title = {Mechanisms and Evaluation of Cross-Layer Fault-Tolerance for Supercomputing},
year = {}
}
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Abstract
Abstract—Reliability is emerging as an important constraint for future microprocessors. Cooperative hardware and software approaches for error tolerance can solve this hardware relia-bility challenge. Cross-layer fault tolerance frameworks expose hardware failures to upper-layers, like the compiler, to help correct faults. Such cooperative approaches require less hardware complexity than masking all faults at the hardware level and are generally more energy efficient. This paper provides a detailed design and an implementation study of cross-layer fault tolerance for supercomputing. Since supercomputers necessarily involve large component counts, they have more frequent failures than consumer electronics and small systems. Conventionally, these systems use redundancy and checkpointing to achieve reliable computing. However, redun-dancy increases acquisition as well as recurring energy costs. This paper describes a simple language-level mechanism coupled with complementary compilation and lightweight hardware error detection that provides efficient reliability and cross-layer fault-tolerance for supercomputers. Our evaluation focuses on strong scaling problems for which we can trade computing power for redundancy. Our results show a range of 1.07x to 2.5x speedup when employing cross-layer error-tolerance compared to conventional full dual modular redundancy (DMR) to contain all errors within hardware. Further, we demonstrate the approach can sustain 7 % to 50 % lower energy. The most important result of this work is qualitative: we can use a simplified hardware design with relaxed architectural correctness guarantees. I.
Keyphrases
cross-layer fault-tolerance hardware relia-bility challenge detailed design large component count error tolerance complementary compilation hardware complexity hardware level cooperative approach small system cross-layer fault tolerance hardware failure lightweight hardware error detection cooperative hardware redun-dancy increase acquisition energy cost important result frequent failure simple language-level mechanism conventional full dual modular redundancy future microprocessor software approach implementation study cross-layer error-tolerance relaxed architectural correctness guarantee cross-layer fault tolerance framework consumer electronics strong scaling problem simplified hardware design energy efficient reliable computing abstract reliability important constraint efficient reliability
