Logic Synthesis of LUT Cascades with Limited Rails -- A Direct Implementation of Multi-Output Functions (2002)
| Venue: | OF IEICE, THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS VOL.102, NO.476(20021121 |
| Citations: | 1 - 0 self |
BibTeX
@TECHREPORT{Mishchenko02logicsynthesis,
author = {Alan Mishchenko and Tsutomu Sasao},
title = {Logic Synthesis of LUT Cascades with Limited Rails -- A Direct Implementation of Multi-Output Functions},
institution = {OF IEICE, THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS VOL.102, NO.476(20021121},
year = {2002}
}
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Abstract
Programmable LUT cascades are used to evaluate multi-output Boolean functions. This paper shows several representations of multi-output functions and introduces a new decomposition algorithm applicable to these representations. The algorithm produces LUT cascades with the limited number of rails, which leads to significantly faster circuits and applicability to large designs. The experiment shows that the proposed algorithm performs well on benchmark functions.
