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@MISC{_,
author = {},
title = {},
year = {}
}
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Abstract
Abstract — Digital signal and image processing applications require a large number of floating point multiplications. For such applications fast multiplication techniques are required to improve the overall system speed. Fast multiplication can be achieved by reducing number of partial products. Canonical signed digit is a recoding technique, which recodes a number with minimum number of non-zero digits. As the number of partial products depends on the number of non-zero digits, by using Canonical recoding, the number of non-zero digits will be reduced, thereby reducing the number of partial products. In this paper, Double-precision floating point multiplication using canonical signed digit is proposed and is compared with Conventional multiplication technique. The design is implemented in Verilog and simulated using Xilinx 9.2 ISE. The results showed that CSD outperforms other algorithm when delay is primary concern.
Keyphrases
non-zero digit partial product point multiplication overall system speed canonical recoding multiplication technique minimum number abstract digital signal fast multiplication large number recoding technique image processing application conventional multiplication technique primary concern
