The Design and Optimization of SOC Test Solutions

The Design and Optimization of SOC Test Solutions (2001)

Cached

Download Links

[www.ida.liu.se]

Other Repositories/Bibliography

DBLP

by Erik Larsson , Zebo Peng , Gunnar Carlsson

Venue:	Proc. of Int. Conf. on Computer-Aided Design
Citations:	6 - 3 self

BibTeX

@INPROCEEDINGS{Larsson01thedesign,
    author = {Erik Larsson and Zebo Peng and Gunnar Carlsson},
    title = {The Design and Optimization of SOC Test Solutions},
    booktitle = {Proc. of Int. Conf. on Computer-Aided Design},
    year = {2001},
    pages = {523--530}
}

Bookmark

OpenURL

Abstract

Abstract 1 We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique are a minimized test schedule fulfilling test conflicts under test power constraints and an optimized design of the test access mechanism. We have implemented the proposed algorithm and performed experiments with several benchmarks and industrial designs to show the usefulness and efficiency of our technique. 1

Citations

106	A distributed BIST control scheme for complex VLSI devices - Zorian - 1993
72	Scheduling Test for VLSI Systems under Power Under Power Constraints - Chou, Saluja, et al. - 1997
51	Minimized Power Consumption for Scan-Based BIST - Gerstend6rfer, Wunderlich - 1999
42	Design of System-on-a-Chip Test Access Architectures Under Place-and-Route and Power Constraints - Chakrabarty - 2000
35	Test scheduling for core-based systems using mixed-integer linear programming - Chakrabarty - 2000
31	Optimal Test Access Architectures for Systemon-a-Chip - Chakrabarty - 2001
29	An Integrated System-On-Chip Test Framework - Larsson, Peng - 2001
24	An ILP Formulation to Optimize Test Access Mechanisms in System-on-a-Chip Testing - Nourani, Papachristou - 2000
21	Test scheduling for core-based systems - Chakrabarty - 1999
18	Scan Chain Design for Test Time Reduction - Aerts, Marinissen - 1998
18	et al. A structured and scalable mechanism for test access to embedded reusable cores - Marinissen - 1998
10	et al., “A comparison of classical scheduling approaches in power-constrained block-test scheduling - Muresan - 2000
4	An Integrated System-Level Design for Testability Methodology - Larsson - 2000
3	et al., “Towards a Standard for Embedded Core Test: An Example - Marinissen - 1999
2	Marinissen et al., Wrapper Design for Embedded Core Test - J - 2000
1	et al., A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures - Benso - 2000
1	et al., Optimization by Simulated - Kirkpatrick - 1983