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Lock-free Dynamically Resizable Arrays

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by Damian Dechev , Peter Pirkelbauer , Bjarne Stroustrup
Citations:12 - 8 self
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BibTeX

@MISC{Dechev_lock-freedynamically,
    author = {Damian Dechev and Peter Pirkelbauer and Bjarne Stroustrup},
    title = {Lock-free Dynamically Resizable Arrays},
    year = {}
}

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Abstract

Abstract. We present a first lock-free design and practical implementation of a dynamically resizable array (vector). The most extensively used container in the C++ Standard Library is vector, offering a combination of dynamic memory management and efficient random access. Our approach is based on a single 32-bit word atomic compare-and-swap (CAS) instruction and our implementation is portable to all systems supporting CAS, and more. It provides a flexible, generic, linearizable and highly parallelizable STL like interface, effective lock-free memory allocation and management, and fast execution. Our current implementation is designed to be most efficient on the most recent multi-core architectures. The test cases on a dual-core Intel processor indicate that our lock-free vector outperforms its lock-based STL counterpart and the latest concurrent vector implementation provided by Intel by a factor of 10. The implemented approach is also applicable across a variety of symmetric multiprocessing (SMP) platforms. The performance evaluation on an 8-way AMD system with non-shared L2 cache demonstrated timing results comparable to the best available lock-based techniques for such systems. The presented design implements the most common STL vector’s interfaces, namely random access read and write, tail insertion and deletion, pre-allocation of memory, and query of the container’s size. Keywords: lock-free, STL, C++, vector, concurrency, real-time systems 1

Keyphrases

lock-free dynamically resizable array    used container    non-shared l2 cache    random access read    standard library    practical implementation    concurrent vector implementation    presented design    dynamic memory management    container size    timing result    fast execution    first lock-free design    dual-core intel processor    lock-based stl counterpart    single 32-bit word atomic compare-and-swap    real-time system    performance evaluation    effective lock-free memory allocation    current implementation    common stl vector interface    lock-free vector    8-way amd system    parallelizable stl    efficient random access    implemented approach    resizable array    recent multi-core architecture    symmetric multiprocessing    test case    available lock-based technique   

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