Evaluation of the raw microprocessor: An exposed-wire-delay architecture for ilp and streams

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Evaluation of the raw microprocessor: An exposed-wire-delay architecture for ilp and streams (2004)

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by Michael Bedford Taylor , Walter Lee , Jason Miller , David Wentzlaff , Ian Bratt , Ben Greenwald , Henry Hoffmann , Paul Johnson , Jason Kim , James Psota , Arvind Saraf , Nathan Shnidman , Volker Strumpen , Matt Frank , Saman Amarasinghe , Anant Agarwal

Venue:	In ISCA
Citations:	82 - 14 self

BibTeX

@INPROCEEDINGS{Taylor04evaluationof,
    author = {Michael Bedford Taylor and Walter Lee and Jason Miller and David Wentzlaff and Ian Bratt and Ben Greenwald and Henry Hoffmann and Paul Johnson and Jason Kim and James Psota and Arvind Saraf and Nathan Shnidman and Volker Strumpen and Matt Frank and Saman Amarasinghe and Anant Agarwal},
    title = {Evaluation of the raw microprocessor: An exposed-wire-delay architecture for ilp and streams},
    booktitle = {In ISCA},
    year = {2004},
    pages = {2--13}
}

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Abstract

This paper evaluates the Raw microprocessor. Raw addresses the challenge of building a general-purpose architecture that performs well on a larger class of stream and embedded computing applications than existing microprocessors, while still running existing ILP-based sequential programs with reasonable performance in the face of increasing wire delays. Raw approaches this challenge by implementing plenty of on-chip resources – including logic, wires, and pins – in a tiled arrangement, and exposing them through a new ISA, so that the software can take advantage of these resources for parallel applications. Raw supports both ILP and streams by routing operands between architecturally-exposed functional units over a point-to-point scalar operand network. This network offers low latency for scalar data transport. Raw manages the effect of wire delays by exposing the interconnect and using software to orchestrate

Keyphrases

raw microprocessor exposed-wire-delay architecture wire delay scalar data transport low latency ilp-based sequential program new isa on-chip resource point-to-point scalar operand network parallel application architecturally-exposed functional unit tiled arrangement general-purpose architecture reasonable performance raw approach

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