@MISC{Goossens_simulationin, author = {K. G. W. Goossens}, title = {Simulation in Hardware Design and Testing}, year = {} }

Share

OpenURL

Abstract

Hardware description languages (hdls) have been used in industry since the 1960s to document and simulate hardware designs. Simulation of hdl descriptions is very useful to find design faults without the need to manufacture the design. A well known drawback of simulation, however, is that the number of input combinations (or test vectors) increases exponentially. For modern designs, it would take years to fully simulate a design. In practice a limited number of test vectors are used to probe the circuit, possibly failing to uncover faults. Formal Hardware Verification Research into formal hardware verification of hardware designs aims to address this problem. A circuit and its specification are given by mathematical descriptions. A mathematical proof system is then used to prove correctness of the design with respect to its specification. Although the hardware verification field is still young, notable achievements include the formally verified viper microprocessor which is manufactured and used commercially. However, most proposed methodologies are not automated, and need considerable expertise to be used. Although formal verification methods remove the exponential explosion occurring for simulation, verification takes substantial time. A severe drawback is that many different notations and tools are employed. Industrial hardware description languages have not yet been used, alienating the hardware verification field from the industrial designers.