Modulo Graph Embedding: Mapping Applications onto Coarse-Grained Reconfigurable Architectures

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Modulo Graph Embedding: Mapping Applications onto Coarse-Grained Reconfigurable Architectures (2006)

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by Hyunchul Park , Kevin Fan , Manjunath Kudlur , Scott Mahlke

Venue:	in CASES ’06: Proceedings of the 2006 international conference on Compilers, architecture
Citations:	23 - 6 self

BibTeX

@INPROCEEDINGS{Park06modulograph,
    author = {Hyunchul Park and Kevin Fan and Manjunath Kudlur and Scott Mahlke},
    title = {Modulo Graph Embedding: Mapping Applications onto Coarse-Grained Reconfigurable Architectures},
    booktitle = {in CASES ’06: Proceedings of the 2006 international conference on Compilers, architecture},
    year = {2006},
    pages = {136--146},
    publisher = {ACM Press}
}

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Abstract

Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing the potential for high computation throughput, scalability, low cost and energy efficiency. CGRAs consist of an array of function units and register files generally organized as a two dimensional grid. The most difficult challenge with deploying CGRAs is compiler scheduling technology that can map software implementations of compute intensive loops onto the array. Traditional schedulers are not suitable because they do not take into account the explicit routing of operand values that is necessary. In essence, the problem of binding operations to time slots and resources is extended to also include explicit routing of operands from producers to consumers. To tackle this problem, this paper introduces a software pipelining technique for mapping loop bodies onto CGRAs, referred to as modulo graph embedding. We leverage graph embedding from graph theory, which is used to draw graphs onto a target space. The loop body is essentially drawn onto the CGRAmesh, subject to modulo resource usage constraints. Modulo graph embedding is effective because it can take into account the communication structure of the loop body during mapping. On average, a compute utilization of 56--68% is achieved for a set of loop kernels across three 4x4 CGRA designs.

Keyphrases

modulo graph embedding coarse-grained reconfigurable architecture mapping application loop body explicit routing hardware platform high computation throughput register file cgras consist software implementation compute utilization loop kernel traditional scheduler cgra design time slot communication structure compute intensive loop function unit modulo graph graph theory energy efficiency dimensional grid low cost difficult challenge operand value target space resource usage constraint

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