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Programmable Logic Device (2005)
| Venue: | Cool Chips VIII, IEEE Symposium on Low-Power and High-Speed Chips |
BibTeX
@INPROCEEDINGS{Stage05programmablelogic,
author = {With An Stage and Kazuyuki Nakamura and Tsutomu Sasao and Munehiro Matsuura and Katsumasa Tanaka and Kenichi Yoshizumi Hui Qin},
title = {Programmable Logic Device},
booktitle = {Cool Chips VIII, IEEE Symposium on Low-Power and High-Speed Chips},
year = {2005}
}
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Abstract
Introduction RAMs and PLAs (Programmable Logic Array) are used for programmable logic devices that realize multiple-output combinational logic functions. However, when the number of inputs and/or outputs for the target function is large, these devices require excessive amounts of hardware. Thus, FPGAs (Field Programmable Gate Arrays) are often used. However, the area and delay for interconnections among logic cells are much larger than those for logic elements. Therefore the prediction of the performance of the FPGA is difficult without complete physical design. To solve these problems, an LUT cascade architecture that is composed of a serial connection of large-scale memories has been developed [1]. The LUT cascade uses relatively larger LUTs (1kb - 1Mb), and the interconnections between LUTs are limited to the adjacent cells in the cascade. This is quite different from the two-dimensional structure of FPGAs with smaller (16b - 64b) LUTs. The large area for the interconnections in an
Keyphrases
programmable logic device logic element serial connection lut cascade large-scale memory programmable logic array large area multiple-output combinational logic function excessive amount introduction ram lut cascade architecture target function field programmable gate array two-dimensional structure complete physical design logic cell adjacent cell
