Verity -- a Formal Verification Program for Custom CMOS Circuits

Verity -- a Formal Verification Program for Custom CMOS Circuits (1994)

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by Andreas Kuehlmann , Arvind Srinivasan , David P. Lapotin

Venue:	IBM JOURNAL OF RESEARCH AND DEVELOPMENT
Citations:	18 - 5 self

BibTeX

@ARTICLE{Kuehlmann94verity--,
    author = {Andreas Kuehlmann and Arvind Srinivasan and David P. Lapotin},
    title = {Verity -- a Formal Verification Program for Custom CMOS Circuits},
    journal = {IBM JOURNAL OF RESEARCH AND DEVELOPMENT},
    year = {1994},
    volume = {39},
    pages = {149--165}
}

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Abstract

In an effort to fully exploit CMOS performance, custom design techniques are used extensively in commercial microprocessor design. However, given the complexity of current generation processors and the necessity for manual designer intervention throughout the design process, proving design correctness is a major concern. In this paper we discuss Verity, a formal verification program for symbolically proving the equivalence between a high-level design specification and a MOS transistor-level implementation. Verity

Citations

2605	Graph-based algorithms for Boolean function manipulation - Bryant - 1986
1207	Symbolic Model Checking - McMillan - 1993
386	Dynamic Variable Ordering for Ordered Binary Decision Diagrams - Rudell - 1993
362	Introduction to VLSI Systems - Mead, Conway - 1980
312	Binary decision diagrams - Akers - 1978
214	Symbolic model checking for sequential circuit verification - Burch - 1994
113	Verification of large synthesized designs - Brand
96	Verification of sequential machines using Boolean functional vectors - Coudert, Berthet, et al. - 1989
86	Formal hardware verification methods: A survey. J Formal Methods Syst Des 1:151–238 - Gupta - 1992
57	Boolean analysis of MOS Circuits - Bryant - 1987
53	Equivalence of free boolean graphs can be decided probabilistically in polynomial time. Information Processing Letters 10(2):80–82 - Blum, Chandra, et al. - 1980
50	Sheffler: COSMOS – a compiled simulator for MOS circuits - Bryant, Beatty, et al.
48	An efficient tool for logic verification based on recursive learning - Kunz, “HANNIBAL - 1993
48	A switch level model and simulator for the MOS digital systems - Bryant - 1984
38	Proving Circuit Correctness using Formal Comparison between Expected and Extracted - Madre, Billon - 1988
26	Variable Ordering Algorithms for Ordered Binary Decision Diagrams and Their Evaluation - Fujita, Fujisawa, et al. - 1993
25	Error Diagnosis for Transistor-level Verification - Kuehlmann, Cheng, et al. - 1992
19	Formal verification of sequential hardware. a tutorial - McFarland - 1993
19	On Verification of Sequential Machines at Differing Levels of Abstraction - Devadas, Ma, et al. - 1988
18	The Yorktown Simulation Engine - Denneau - 1982
17	Extraction of Gate Level Models from Transistor Circuits by Four-Valued - Bryant - 1991
16	Probabilistic Design Verification - Jain, Bitner, et al. - 1991
13	Boolean comparison of hardware and flowcharts - Smith, Bahnsen, et al. - 1982
12	Comparing Layouts with HDL Models: A Formal Verification Technique - Kam, Subrahmanyam - 1992
10	Design Verification System for Large-scale LSI Designs - Monachino - 1982
9	A Second Generation Layout Validation Tool - Ebeling - 1988
7	Logic Equations for MOSFET Circuits - Ditlow, Donath, et al. - 1983
7	P.Banerjee, “Functional abstraction of logic gates for switch-level simulation - Blaauw, Saab - 1991
7	Probabilistic Construction and Manipulation of Free Boolean Diagrams - Shen, Devadas, et al. - 1993
6	Specification and verification using higher-order logic - Hanna, Daeche - 1985
5	Hardware verification - Roth - 1977
4	A Hardware Architecture for Switch-Level Simulation - Dally, Bryant - 1985
4	Mapping switch-level simulation onto gate-level hardware accelerators," 28th DAC - Jain, Bryant - 1991
2	The EVE companion simulator - Beece, Damiano, et al. - 1990
2	Simulating pass transistor circuits using logic simulation machines - Barzilai, Huisman, et al. - 1983
2	Switch-Level Simulation of VLSI Using a Special-Purpose, Data-Driven Computer - Frank - 1985
2	Hardware verification using high-order logic,” in From HDL Descriptions to Guaranteed Correct Circuit Designs - Camilleri, Gordon, et al. - 1987
2	The necessity of closed loops in minimal combinational circuits - Kauz - 1970
2	Analysis of cyclic combinatorial circuits - Malik - 1993