Cyclic Stress Tests for Full Scan Circuits

Cyclic Stress Tests for Full Scan Circuits (1995)

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by Vinay Dabholkar , Sreejit Chakravarty , Farid Najm , Janak Patel

Venue:	IEEE VLSI Test Syposium
Citations:	2 - 2 self

BibTeX

@ARTICLE{Dabholkar95cyclicstress,
    author = {Vinay Dabholkar and Sreejit Chakravarty and Farid Najm and Janak Patel},
    title = {Cyclic Stress Tests for Full Scan Circuits},
    journal = {IEEE VLSI Test Syposium},
    year = {1995}
}

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Abstract

To ensure the production of reliable circuits and fully testable unpackaged dies for MCMs burn-in, both dynamic and monitored, remains a feasible option. During this burn-in process the circuit needs to be stressed for an extended period of time. This requires computation of cyclic input sequences to stress the circuit. A taxanomy of stress related problems for full scan circuits is presented. It is shown that there are efficient ways to compute the sequences for most variations of monitored burn-in problems. The difficulty of computing stress tests for dynamic burn-in problems is discussed. Preliminary experimental results on ISCAS89 benchmark circuits are presented. 1 Introduction Growing size of VLSI circuits, high transistor density and advent of MCM technology is making production of reliable chips a challenging task. Functional testing and various kind of burn-ins have been used to guarantee greater reliability. It has been observed that potential advantages in circuit density a...

Keyphrases

full scan circuit cyclic stress test circuit density mcm technology iscas89 benchmark circuit monitored burn-in problem efficient way feasible option burn-in process reliable circuit extended period potential advantage functional testing testable unpackaged dy preliminary experimental result various kind stress test high transistor density cyclic input sequence dynamic burn-in problem challenging task vlsi circuit reliable chip mcms burn-in