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A 225MHz resonant clocked ASIC chip (2003)
| Venue: | in Proceedings of International Symposium on Low-Power Electronics and Design |
| Citations: | 4 - 2 self |
BibTeX
@INPROCEEDINGS{Ziesler03a225mhz,
author = {Conrad H. Ziesler and Joohee Kim and Visvesh S. Sathe and Marios C. Papaefthymiou},
title = {A 225MHz resonant clocked ASIC chip},
booktitle = {in Proceedings of International Symposium on Low-Power Electronics and Design},
year = {2003},
pages = {48--53}
}
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Abstract
We have recently designed, fabricated, and successfully tested an experimental chip that validates a novel method for reducing clock dissipation through energy recovery. Our approach includes a single-phase sinusoidal clock signal, an L-C resonant sinusoidal clock generator, and an energy recovering flip-flop. Our chip comprises a dual-mode ASIC with two independent clock systems, one conven-tional and one energy recovering, and was fabricated in a 0.25µm bulk CMOS process. The ASIC computes a pipelined discrete wavelet transform with self-test and contains over 3500 gates. We have verified correct functionality and obtained power measure-ments in both modes of operation for frequencies up to 225MHz. In the energy recovering mode, our power measurements account for all of the dissipation factors, including the operation of the in-tegrated resonant clock generator, and show a net energy savings over the conventional mode of operation. For example, at 115MHz, measured dissipation is between 60 % and 75 % of the conventional mode, depending on primary input activity. To our knowledge, this is the first ever published account of a direct experimentally-measured comparison between a complete energy recovering ASIC chip and its conventional implementation correctly operating in sil-icon at frequencies exceeding 100MHz.
Keyphrases
asic chip conventional mode energy recovering clock dissipation dissipation factor experimental chip direct experimentally-measured comparison obtained power measure-ments pipelined discrete wavelet transform net energy saving energy recovery dual-mode asic complete energy correct functionality l-c resonant sinusoidal clock generator novel method bulk cmos process power measurement conventional implementation independent clock system in-tegrated resonant clock generator single-phase sinusoidal clock signal primary input activity
