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Microarchitecture optimizations for exploiting memory-level parallelism (2004)
| Venue: | In ISCA-31 |
| Citations: | 97 - 3 self |
BibTeX
@INPROCEEDINGS{Chou04microarchitectureoptimizations,
author = {Yuan Chou and Brian Fahs and Santosh Abraham and Sun Microsystems},
title = {Microarchitecture optimizations for exploiting memory-level parallelism},
booktitle = {In ISCA-31},
year = {2004}
}
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Abstract
The performance of memory-bound commercial applications such as databases is limited by increasing memory latencies. In this paper, we show that exploiting memory-level parallelism (MLP) is an effective approach for improving the performance of these applications and that microarchitecture has a profound im-pact on achievable MLP. Using the epoch model of MLP, we rea-son how traditional microarchitecture features such as out-of-order issue and state-of-the-art microarchitecture techniques such as runahead execution affect MLP. Simulation results show that a moderately aggressive out-of-order issue processor improves MLP over an in-order issue processor by 12-30%, and that ag-gressive handling of loads, branches and serializing instructions is needed to attain the full benefits of large out-of-order instruction windows. The results also show that a processor’s issue window and reorder buffer should be decoupled to exploit MLP more effi-ciently. In addition, we demonstrate that runahead execution is highly effective in enhancing MLP, potentially improving the MLP of the database workload by 82 % and its overall performance by 60%. Finally, our limit study shows that there is considerable headroom in improving MLP and overall performance by imple-menting effective instruction prefetching, more accurate branch prediction and better value prediction in addition to runahead ex-ecution. 1
Keyphrases
memory-level parallelism microarchitecture optimization overall performance state-of-the-art microarchitecture technique considerable headroom full benefit database workload runahead execution affect mlp out-of-order issue runahead execution accurate branch prediction achievable mlp in-order issue processor traditional microarchitecture feature reorder buffer effective approach epoch model limit study processor issue window ag-gressive handling imple-menting effective instruction prefetching aggressive out-of-order issue processor value prediction large out-of-order instruction window memory latency profound im-pact simulation result memory-bound commercial application
