Worst-Case Timing Analysis of Concurrently Executing DMA I/O and Programs

Worst-Case Timing Analysis of Concurrently Executing DMA I/O and Programs (1997)

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by Tai-Yi Huang , Jane W. -s. Liu

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@MISC{Huang97worst-casetiming,
    author = {Tai-Yi Huang and Jane W. -s. Liu},
    title = {Worst-Case Timing Analysis of Concurrently Executing DMA I/O and Programs},
    year = {1997}
}

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Abstract

od. A cycle-stealing DMA I/O task is allowed to proceed only when the CPU does not need the system bus. As a result, the execution time of a cycle-stealing DMA I/O task is affected by a set of CPU tasks which execute concurrently with the I/O task. We discuss the problem of bounding the WCET of a cycle-stealing DMA I/O task under a workload which consists of a set of independent CPU tasks. Each CPU task has an arbitrary release time. We use the dynamic programming technique to bound the WCET of the I/O task. iii To my parents iv Acknowledgments I would like to express my deepest gratitude to my thesis advisor, Professor Jane Liu, for her constant guidance and support, without which this thesis has not been possible. I also thank the other members of my committee, Professors Rajesh Gupta, Janak Patel and David Padua, for their time and interest. I am grateful to all the members of the real-time research group: Zhong Deng, Wu Feng, Mark Gardner, Rhan Ha, David Hull, I

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