Complexity-effective superscalar processors

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Complexity-effective superscalar processors (1997)

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by Subbarao Palacharla , J. E. Smith, et al.

Venue:	IN PROCEEDINGS OF THE 24TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
Citations:	467 - 5 self

BibTeX

@INPROCEEDINGS{Palacharla97complexity-effectivesuperscalar,
    author = {Subbarao Palacharla and J. E. Smith and et al.},
    title = {Complexity-effective superscalar processors},
    booktitle = {IN PROCEEDINGS OF THE 24TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE},
    year = {1997},
    pages = {206--218},
    publisher = {}
}

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Abstract

The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, instruction window wakeup and selection logic, and operand bypassing are ana-lyzed. Each is modeled and Spice simulated for feature sizes of 0:8m, 0:35m, and 0:18m. Performance results and trends are expressed in terms of issue width and window size. Our analysis indicates that window wakeup and selection logic as well as operand bypass logic are likely to be the most critical in the future. A microarchitecture that simplifies wakeup and selection logic is proposed and discussed. This implementation puts chains of dependent instructions into queues, and issues instructions from multiple queues in parallel. Simulation shows little slowdown as compared with a completely flexible issue window when performance is measured in clock cycles. Furthermore, because only instructions at queue heads need to be awakened and selected, issue logic is simpli-fied and the clock cycle is faster – consequently overall performance is improved. By grouping dependent instructions together, the proposed microarchitecture will help minimize performance degradation due to slow bypasses in future wide-issue machines.

Keyphrases

complexityeffective superscalar processor selection logic clock cycle issue instruction operand bypass logic feature size hardware complexity de-pendent instruction analysis in-dicates queue head pro-posed microarchitecture performance result window size instruction win-dow wakeup flexible issue window mul-tiple queue performance degrada-tion overall performance specific area future wide-issue machine register renaming dependent instruction issue width performance tradeoff generic superscalar pipeline clock speed

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