Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays (1996)
| Venue: | Journal of VLSI Design |
| Citations: | 25 - 2 self |
BibTeX
@ARTICLE{Brown96segmentedrouting,
author = {Stephen Brown and Muhammad Khellah and Guy Lemieux},
title = {Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays},
journal = {Journal of VLSI Design},
year = {1996},
volume = {4},
pages = {275--291}
}
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Abstract
This paper addresses several issues involved for routing in Field-Programmable Gate Arrays (FPGAs) that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measuring the effects that various parameters of the CAD tools have on the implementation of the circuits. A two-stage routing strategy of global followed by detailed routing is used, and the effects of both of these CAD stages are discussed, with emphasis on detailed routing. We present a new detailed routing algorithm designed specifically for the types of routing structures found in the most recent generation of FPGAs, and show that the new algorithm achieves significantly better results than previously published FPGA routers with respect to the speed-performance of implemented circuits. The experiments presented in this paper address both of the key metrics for FPGA routing tools, namely the eff...
