Efficient Ordering of State Variables and Transition Relation Partitions in Symbolic Model Checking

Efficient Ordering of State Variables and Transition Relation Partitions in Symbolic Model Checking (1997)

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by Mathias Block , Clemens Gröpl , Harry Preuß , Hans Jürgen Prömel , Anand Srivastav

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BibTeX

@MISC{Block97efficientordering,
    author = {Mathias Block and Clemens Gröpl and Harry Preuß and Hans Jürgen Prömel and Anand Srivastav},
    title = {Efficient Ordering of State Variables and Transition Relation Partitions in Symbolic Model Checking},
    year = {1997}
}

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Abstract

Among the main algorithmic problems in the verification of sequential circuits are the computation of good orders of state variables and transition relation partitions. Existing model checking packages like SMV from CMU, VIS from Berkeley or Rulebase from IBM Haifa provide variants of Rudell's sifting algorithm for the variable ordering problem and greedy-type algorithms for the partition ordering problem. For both problems, we give new simulated annealing based algorithms and we provide a model checking program called VERIFY which is based on SMV. The impact of our approach is demonstrated on industrial arbiter circuits and ISCAS '89 benchmarks. In particular on large industrial circuits our algorithms show a better space/time performance than previously given heuristics.

Citations

1207	Symbolic Model Checking - McMillan - 1993
421	Efficient implementation of a BDD package - Brace, Rudell, et al. - 1990
386	Dynamic Variable Ordering for Ordered Binary Decision Diagrams - Rudell - 1993
333	Simulated Annealing and Boltzmann Machines - Aarts, Korts - 1989
214	Symbolic model checking for sequential circuit verification - Burch - 1994
169	Sequential Circuit Verification Using Symbolic Model Checking - Burch, Clarke, et al. - 1990
146	Symbolic model checking with partitioned transition relations - Burch - 1991
132	Logic verification using binary decision diagrams in a logic synthesis environment - Malik, Wang, et al. - 1988
130	Implicit State Enumeration of Finite State Machines using BDD's - Touati - 1990
106	On variable ordering of binary decision diagrams for the application of multi-level logic synthesis - Fujita, Matsunaga, et al. - 1991
103	VIS: A System for Verification and Synthesis - Brayton, Hachtel, et al. - 1996
90	Supowit : Finding an optimal variable ordering for binary decision diagrams - Friedman, J - 1990
83	Evaluation and improvements of boolean comparison method based on binary decision diagrams - Fujita, Fujisawa, et al. - 1988
59	RuleBase: an industry-oriented formal verification tool - Beer, Ben-David, et al. - 1996
56	The SMV system - McMillan - 1992
56	Efficient BDD Algorithms for FSM Synthesis and Verification - Ranjan, Aziz, et al. - 1995
54	Efficient model checking by automated ordering of transition relation partitions - Geist, Beer - 1994
35	Heuristics to compute variable orderings for efficient manipulation of ordered binary decision diagrams - Butler, Ross, et al. - 1991
32	Functional approaches to generating orderings for efficient symbolic representations - Mercer, Kapur, et al. - 1992
26	Formal Verification of the Encore Gigamax Cache Consistency Protocol - McMillan, Schwalbe - 1991
18	Speeding Up Variable Reordering of OBDDs - Meinel, Slobodova - 1997
18	Fast functional evaluation of candidate OBDD variable ordering - Ross, Butler, et al. - 1991
17	Representing Circuits More Efficiently - Burch, Clarke, et al. - 1991
17	Variable ordering and selection for FSM traversal - Jeong, Plessier, et al. - 1991
4	Variable orderings for obdds, simulated annealing, and the hidden weighted bit function - Bollig, Lobbing, et al. - 1996
4	Yajima: Minimization of Binary Decision Diagrams Based on Exchanges of Variables - Ishiura, Sawada, et al. - 1991