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Analyzing CUDA workloads using a detailed gpu simulator (2009)
| Venue: | In Proceedings of the International Symposium on Performance Analysis of Systems and Software |
| Citations: | 168 - 8 self |
BibTeX
@INPROCEEDINGS{Bakhoda09analyzingcuda,
author = {Ali Bakhoda and George L. Yuan and Wilson W. L. Fung and Henry Wong and Tor M. Aamodt},
title = {Analyzing CUDA workloads using a detailed gpu simulator},
booktitle = {In Proceedings of the International Symposium on Performance Analysis of Systems and Software},
year = {2009},
pages = {163--174}
}
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Abstract
Modern Graphic Processing Units (GPUs) provide suffi-ciently flexible programming models that understanding their performance can provide insight in designing tomorrow’s manycore processors, whether those are GPUs or other-wise. The combination of multiple, multithreaded, SIMD cores makes studying these GPUs useful in understanding trade-offs among memory, data, and thread level parallelism. While modern GPUs offer orders of magnitude more raw comput-ing power than contemporary CPUs, many important ap-plications, even those with abundant data level parallelism, do not achieve peak performance. This paper characterizes several non-graphics applications written in NVIDIA’s CUDA programming model by running them on a novel detailed microarchitecture performance simulator that runs NVIDIA’s parallel thread execution (PTX) virtual instruction set. For this study, we selected twelve non-trivial CUDA applications demonstrating varying levels of performance improvement on GPU hardware (versus a CPU-only sequential version of the application). We study the performance of these applica-tions on our GPU performance simulator with configurations comparable to contemporary high-end graphics cards. We characterize the performance impact of several microarchitec-ture design choices including choice of interconnect topology, use of caches, design of memory controller, parallel work-load distribution mechanisms, and memory request coalescing hardware. Two observations we make are (1) that for the appli-cations we study, performance is more sensitive to interconnect bisection bandwidth rather than latency, and (2) that, for some applications, running fewer threads concurrently than on-chip resources might otherwise allow can improve performance by reducing contention in the memory system. 1.
Keyphrases
cuda workload detailed gpu simulator virtual instruction set memory system tomorrow manycore processor performance improvement understanding trade-off on-chip resource flexible programming model twelve non-trivial cuda application novel detailed microarchitecture performance simulator contemporary cpu gpu hardware nvidia cuda peak performance several microarchitec-ture design choice varying level thread execution gpu performance simulator raw comput-ing power memory request abundant data level parallelism thread level parallelism cpu-only sequential version several non-graphics application gpus useful interconnect topology modern gpus offer order many important ap-plications contemporary high-end graphic card parallel work-load distribution mechanism memory controller performance impact modern graphic processing unit
