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Exploiting choice : Instruction fetch and issue on an implementable simultaneous MultiThreading processor (1996)
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| Venue: | In Proceedings of the 23 rd Annual International Symposium on Computer Architecure |
| Citations: | 2 - 0 self |
BibTeX
@INPROCEEDINGS{Lo96exploitingchoice,
author = {Jack L. Lo and Rebecca L. Stammy},
title = {Exploiting choice : Instruction fetch and issue on an implementable simultaneous MultiThreading processor},
booktitle = {In Proceedings of the 23 rd Annual International Symposium on Computer Architecure},
year = {1996},
pages = {191--202},
publisher = {ACM Press}
}
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Abstract
Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance potential of si-multaneous multithreading, based on a somewhat idealized model. In this paper we show that the throughput gains from simultaneous multithreading can be achieved without extensive changes to a con-ventional wide-issue superscalar, either in hardware structures or sizes. We present an architecture for simultaneous multithreading that achieves three goals: (1) it minimizes the architectural impact on the conventional superscalar design, (2) it has minimal perfor-mance impact on a single thread executing alone, and (3) it achieves significant throughput gains when running multiple threads. Our simultaneous multithreading architecture achieves a throughput of 5.4 instructions per cycle, a 2.5-fold improvement over an unmod-ified superscalar with similar hardware resources. This speedup is enhanced by an advantage of multithreading previously unexploited in other architectures: the ability to favor for fetch and issue those threads most efficiently using the processor each cycle, thereby providing the “best ” instructions to the processor. 1
Keyphrases
simultaneous multithreading implementable simultaneous multithreading processor instruction fetch extensive change similar hardware resource hardware structure multiple independent thread unmod-ified superscalar previous work minimal perfor-mance impact multiple instruction significant throughput gain idealized model si-multaneous multithreading performance potential conventional superscalar design throughput gain architectural impact simultaneous multithreading architecture 5-fold improvement con-ventional wide-issue superscalar single thread
