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Design and implementation of a hot-potato switch in network on chip (2002)
| Venue: | Master of Science thesis, Laboratory of Electronics and Computer Systems, Royal Institute of Technology (KTH |
| Citations: | 32 - 3 self |
BibTeX
@INPROCEEDINGS{Nilsson02designand,
author = {Erland Nilsson and Supervisors Axel Jantsch},
title = {Design and implementation of a hot-potato switch in network on chip},
booktitle = {Master of Science thesis, Laboratory of Electronics and Computer Systems, Royal Institute of Technology (KTH},
year = {2002}
}
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Abstract
As the number of transistor functions on a single chip increases, applied systems becomes more complex and the challenge of developing applications in short time is critical. The design of chips for applications used in for example telecommu-nication demands high performance and reliability, while the time-to-market factor is kept to a minimum. To meet this challenge, a design methodology is required which allows reuse of previously made designs. Resources are identied from previous designs. A resource can be any kind of Intellectual Property, for example, a processor element, an I/O-element, or various memory types. Many resources can form a network mesh. The network model re ected is called Network on Chip, in short NoC. In the NoC, the computational resources are distributed all over the chip, organised in regions, connected together over a communication network. The network consists of a two-dimensional mesh of switch-resource pairs. This master thesis is an attempt of implementing the NoC switch in synthesisable VHDL.
Keyphrases
hot-potato switch computational resource two-dimensional mesh synthesisable vhdl intellectual property many resource short time noc switch master thesis network mesh short noc switch-resource pair communication network previous design network model re design methodology single chip increase various memory type processor element time-to-market factor transistor function example telecommu-nication demand high performance
