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A Technique for Low Energy Mapping and Routing in Network-on-Chip Architectures (2005)
| Venue: | In ISLPED |
| Citations: | 21 - 1 self |
BibTeX
@INPROCEEDINGS{Srinivasan05atechnique,
author = {Krishnan Srinivasan and Karam S. Chatha},
title = {A Technique for Low Energy Mapping and Routing in Network-on-Chip Architectures},
booktitle = {In ISLPED},
year = {2005}
}
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Abstract
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh based topolo-gies requires mapping of cores to router ports, and routing of traffic traces such that the bandwidth and latency constraints are satis-fied. We present a novel automated design technique that solves the mesh based NoC design problem with an objective of minimiz-ing the communication energy. In contrast to existing research that only take bandwidth constraints as inputs, our technique solves the NoC design problem in the presence of bandwidth as well as la-tency constraints. We compare our technique with a recent work called NMAP and an optimal MILP based formulation. We prove that the complexity of our technique is lower than that of NMAP. For the latency constrained case, while NMAP fails on most test cases, our technique is able to generate high quality results. In comparison to the MILP formulation, the results produced by our technique are within 14 % of the optimal.
Keyphrases
low energy mapping network-on-chip architecture noc design problem milp formulation la-tency constraint design technique communication energy latency constraint traffic trace global communication challenge high quality result nanoscale technology optimal milp test case bandwidth constraint noc design recent work
