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Memory access buffering in multiprocessors (1986)
| Venue: | In Proceedings of the 13th Annual International Symposium on Computer Architecture |
| Citations: | 254 - 4 self |
BibTeX
@INPROCEEDINGS{Dubois86memoryaccess,
author = {Michel Dubois and Chrlstoph Scheurich and Faye Briggs},
title = {Memory access buffering in multiprocessors},
booktitle = {In Proceedings of the 13th Annual International Symposium on Computer Architecture},
year = {1986},
pages = {434--442}
}
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Abstract
In highly-pipelined machines, instructions and data are prefetched and buffered in both the processor and the cache. This is done to reduce the average memory access la-tency and to take advantage of memory interleaving. Lock-up free caches are designed to avoid processor blocking on a cache miss. Write buffers are often included in a pipelined machine to avoid processor waiting on writes. In a shared memory multiprocessor, there are more advantages in buffering memory requests, since each memory access has to traverse the memory- processor interconnection and has to compete with memory requests issued by different processors. Buffering, however, can cause logical problems in multipro-cessors. These problems are aggravated if each processor has a private memory in which shared writable data may be present, such as in a cache-based system or in a system with a distributed global memory. In this paper, we analyze the benefits and problems associated with the buffering of memory requests in shared memory multiprocessors. We show that the logical problem of buffering is directly related to the problem of synchronization. A simple model is presented to evaluate the performance improvement result-ing from buffering. 1.
Keyphrases
memory access buffering memory request logical problem shared memory multiprocessor private memory memory interleaving memory processor interconnection different processor lock-up free cache highly-pipelined machine distributed global memory write buffer simple model writable data pipelined machine average memory access la-tency cache miss performance improvement result-ing memory access cache-based system
