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Exploring Latency-Power Tradeoffs in Deep Nonvolatile Memory Hierarchies
| Citations: | 2 - 0 self |
BibTeX
@MISC{Yoon_exploringlatency-power,
author = {Doe Hyun Yoon and Tobin Gonzalez and Parthasarathy Ranganathan and Robert S. Schreiber},
title = {Exploring Latency-Power Tradeoffs in Deep Nonvolatile Memory Hierarchies},
year = {}
}
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Abstract
To handle the demand for very large main memory, we are likely to use nonvolatile memory (NVM) as main memory. NVM main memory will have higher latency than DRAM. To cope with this, we advocate a less-deep cache hierar-chy based on a large last-level, NVM cache. We develop a model that estimates average memory access time and power of a cache hierarchy. The model is based on captured application behavior, an analytical power and performance model, and circuit-level memory models such as CACTI and NVSim. We use the model to explore the cache hierarchy design space and present latency-power tradeoffs for mem-ory intensive SPEC benchmarks and scientific applications. The results indicate that a flattened hierarchy lowers power and improves average memory access time.
Keyphrases
latency-power tradeoff deep nonvolatile memory hierarchy average memory access time large main memory cache hierarchy nvm main memory main memory less-deep cache hierar-chy analytical power nvm cache scientific application performance model flattened hierarchy lower power circuit-level memory model cache hierarchy design space captured application behavior nonvolatile memory present latency-power tradeoff large last-level mem-ory intensive spec benchmark
