Timed Circuit Verification Using TEL Structures

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Timed Circuit Verification Using TEL Structures (2001)

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by Wendy Belluomini , Chris J. Myers , H. Peter Hofstee

Venue:	IEEE Transactions on Computer-Aided Design of Integrated Circuits
Citations:	16 - 6 self

BibTeX

@ARTICLE{Belluomini01timedcircuit,
    author = {Wendy Belluomini and Chris J. Myers and H. Peter Hofstee},
    title = {Timed Circuit Verification Using TEL Structures},
    journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits},
    year = {2001}
}

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Abstract

Abstract—Recent design examples have shown that significant performance gains are realized when circuit designers are allowed to make aggressive timing assumptions. Circuit correctness in these aggressive styles is highly timing dependent and, in industry, they are typically designed by hand. In order to automate the process of designing and verifying timed circuits, algorithms for their synthesis and verification are necessary. This paper presents timed event/level (TEL) structures, a specification formalism for timed circuits that corresponds directly to gate-level circuits. It also presents an algorithm based on partially ordered sets to make the state-space exploration of TEL structures more tractable. The combination of the new specification method and algorithm significantly improves efficiency for gate-level timing verification. Results on a number of circuits, including many from the recently published gigahertz unit Test Site (guTS) processor from IBM indicate that modules of significant size can be verified using a level of abstraction that preserves the interesting timing properties of the circuit. Accurate circuit level verification allows the designer to include less margin in the design, which can lead to increased performance. I.

Keyphrases

timed circuit circuit designer specification formalism significant size state-space exploration timed event level aggressive style abstract recent design example new specification method circuit correctness aggressive timing assumption gate-level timing verification gigahertz unit test site significant performance gain gate-level circuit interesting timing property accurate circuit level verification increased performance timing dependent

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