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On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis (2003)
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BibTeX
@MISC{Adya03onwhitespace,
author = {Saurabh N. Adya and Igor L. Markov and Paul G. Villarrubia},
title = {On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis},
year = {2003}
}
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Abstract
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible gate sizing, net buffering and detail placement require a certain amount of unused space in every region of the die. The need for "local" whitespace is further emphasized by temperature and power-density limits. Another requirement, the stability of placement results from run to run, is important to the convergence of physical synthesis loops. Indeed, logic resynthesis targetting local congestion in a given placement or particular critical paths may be irrelevant for another placement produced by the same or a different layout tool.
Keyphrases
physical synthesis mixed-size placement different layout tool large-scale standard-cell placement algorithm local whitespace net buffering flexible gate sizing placement result local congestion physical synthesis loop certain amount incremental change power-density limit logic resynthesis unused space particular critical path detail placement
