SELF-TESTING SOC WITH REDUCED MEMORY REQUIREMENTS AND MINIMIZED HARDWARE OVERHEAD
BibTeX
@MISC{_self-testingsoc,
author = {},
title = {SELF-TESTING SOC WITH REDUCED MEMORY REQUIREMENTS AND MINIMIZED HARDWARE OVERHEAD},
year = {}
}
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Abstract
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores designed according to the IEEE 1500 standard. The system spares memory and keeps acceptable test access mechanism requirements. The diagnostic system uses a built-in processor for test control, the embedded RAM memory for storing both the compressed test vectors and the partial reconfiguration bit streams and the FPGA (Fieldprogrammable gate array) part of the chip for the wrapped cores implementation. The highly compressed test vectors are transferred from the memory to those selected cores that are reconfigured into the embedded tester cores. The patterns are decompressed within the internal scan chains of the embedded tester cores and they are simultaneously fed into the parallel scan chains of the cores under test through Test Access Mechanism (TAM) and standard wrappers. After having tested the first cores under test the TAM of the System on Chip (SoC) is partially reconfigured with the help of the partial reconfiguration bitstreams stored in the RAM memory and the till now untested cores are tested by those cores that start to serve as embedded testers. By this traveling reconfiguration and testing the whole circuit can be tested. For test data compression we use a test pattern compaction and compression algorithm called COMPAS. It reorders and compresses test patterns previously generated in an Automatic Test Pattern Generation (ATPG) in such a way that they are well suited for decompression by the scan chains in the embedded tester cores. The algorithm compresses the test patterns by overlapping patterns originally generated by an ATPG. The volume of test data stored in the embedded RAM is
Keyphrases
embedded tester core compressed test vector test pattern standard wrapper test data wrapped core implementation parallel scan chain scan chain compression algorithm ram memory embedded tester first core untested core automatic test pattern generation embedded ram built-in processor diagnostic system test pattern compaction system application partial reconfiguration bit stream partial reconfiguration bitstreams test control whole circuit built-in diagnostic system fieldprogrammable gate array at94k fpslic test access mechanism internal scan chain embedded ram memory test data compression experimental result acceptable test access mechanism requirement
