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doi:10.1155/2008/562326 Research Article DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency (2007)
BibTeX
@MISC{Pillement07doi:10.1155/2008/562326research,
author = {Sébastien Pillement and Olivier Sentieys and Raphaël David},
title = {doi:10.1155/2008/562326 Research Article DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency},
year = {2007}
}
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Abstract
Flexibility becomes a major concern for the development of multimedia and mobile communication systems, as well as classical high-performance and low-energy consumption constraints. The use of general-purpose processors solves flexibility problems but fails to cope with the increasing demand for energy efficiency. This paper presents the DART architecture based on the functionallevel reconfiguration paradigm which allows a significant improvement in energy efficiency. DART is built around a hierarchical interconnection network allowing high flexibility while keeping the power overhead low. To enable specific optimizations, DART supports two modes of reconfiguration. The compilation framework is built using compilation and high-level synthesis techniques. A 3G mobile communication application has been implemented as a proof of concept. The energy distribution within the architecture and the physical implementation are also discussed. Finally, the VLSI design of a 0.13 x2009μm CMOS SoC implementing a specialized DART cluster is presented. Copyright © 2008 Sébastien Pillement et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. 1.
Keyphrases
functional-level reconfigurable architecture high energy efficiency research article dart energy efficiency original work energy distribution compilation framework dart architecture high flexibility significant improvement specialized dart cluster mobile communication application creative common attribution license functionallevel reconfiguration paradigm physical implementation classical high-performance vlsi design mobile communication system unrestricted use major concern specific optimization flexibility problem bastien pillement low-energy consumption constraint high-level synthesis technique general-purpose processor hierarchical interconnection network x2009 cmos soc open access article
