An Efficient Parallel Algorithm for the Layered Planar Monotone Circuit Value Problem (1993)
| Venue: | Proc. 1st European Symp. on Algorithms, Springer-Verlag, LNCS 726 |
BibTeX
@INPROCEEDINGS{Ramachandran93anefficient,
author = {Vijaya Ramachandran and Honghua Yang},
title = {An Efficient Parallel Algorithm for the Layered Planar Monotone Circuit Value Problem},
booktitle = {Proc. 1st European Symp. on Algorithms, Springer-Verlag, LNCS 726},
year = {1993},
pages = {321--332}
}
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Abstract
A planar monotone circuit (PMC) is a Boolean circuit that can be embedded in the plane and that contains only AND and OR gates. A layered PMC is a PMC in which all input nodes are in the external face, and the gates can be assigned to layers in such a way that every wire goes between gates in successive layers. Goldschlager, Cook & Dymond and others have developed NC 2 algorithms to evaluate a layered PMC when the output node is in the same face as the input nodes. These algorithms require a large number of processors(\Omega\Gamma n 6 ), where n is the size of the input circuit). In this paper, we give an efficient parallel algorithm that evaluates a layered PMC of size n in O(log 2 n) time using only a linear number of processors on an EREW PRAM. Our parallel algorithm is the best possible to within a polylog factor, and is a substantial improvement over the earlier algorithms for the problem. This work was supported in part by Texas Advanced Research Projects Grant ...
