DMCA
Retiming Synchronous Circuitry (1991)
| Venue: | ALGORITHMICA |
| Citations: | 375 - 3 self |
BibTeX
@MISC{Leiserson91retimingsynchronous,
author = {Charles E. Leiserson and James B. Saxe},
title = { Retiming Synchronous Circuitry },
year = {1991}
}
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Abstract
This paper describes a circuit transformation called retiming in which registers are added at some points in a circuit and removed from others in such a way that the functional behavior of the circuit as a whole is preserved. We show that retiming can be used to transform a given synchronous circuit into a more efficient circuit under a variety of different cost criteria. We model a circuit as a graph in which the vertex set Visa collection of combinational logic elements and the edge set E is the set of interconnections, each of which may pass through zero or more registers. We give an 0(|V| |E| lg|V|) algorithm for determining an equivalent retimed circuit with the smallest possible clock period. We show that the problem of determining an equivalent retimed circuit with minimum state (total number of registers) is polynomial-time solvable. This result yields a polynomial-time optimal solution to the problem of pipelining combinational circuitry with minimum register cost. We also give a characterization of optimal retiming based on an efficiently solvable mixed-integer linear-programming problem.
Keyphrases
synchronous circuitry possible clock period synchronous circuit different cost criterion combinational logic element polynomial-time optimal solution functional behavior efficient circuit total number combinational circuitry circuit transformation solvable mixed-integer linear-programming problem visa collection minimum state minimum register cost
