DMCA
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique
BibTeX
@MISC{Fuketa_minimizingenergy,
author = {Hiroshi Fuketa and Koji Hirairi and Tadashi Yasufuku and Makoto Takamiya and Masahiro Nomura and Hirofumi Shinohara and Takayasu Sakurai},
title = {Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique},
year = {}
}
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Abstract
Abstract — To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (VDD) of flip-flops (FFs) from that of combinational circuits, called the higher voltage FF (HVFF). Although VDD scaling can reduce the energy, the minimum operating voltage (VDDmin) of FFs prevents the operation at the optimum supply voltage that minimizes the energy, because the VDDmin of FFs is higher than the optimum supply voltage. In HVFF, the VDD of combinational logic gates is reduced below the VDDmin of FFs while keeping the VDD of FFs at their VDDmin. This makes it possible to minimize the energy without power and delay penalties at the nominal supply voltage (1.2 V) as well as without FF topological difications. A 16-bit integer unit with HVFF is fabricated in a 65-nm CMOS process, and measurement results show that HVFF reduces the minimum energy by 13% compared with the conventional operation, which is 1/10 times smaller than the energy at the nominal supply voltage. Index Terms — Minimum operating voltage, subthreshold circuits, variations.
Keyphrases
integer unit vddmin-aware dual supply voltage technique higher voltage optimum supply voltage nominal supply voltage voltage ff ff topological difications 16-bit integer unit measurement result subthreshold circuit power supply voltage combinational logic gate minimum operating voltage circuit design technique energy-efficient operation delay penalty minimum energy index term minimum operating voltage conventional operation combinational circuit 65-nm cmos process
