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Tradeoffs in Two-Level On-Chip Caching (1993)
| Venue: | In Proceedings of the 21st Annual International Symposium on Computer Architecture |
| Citations: | 104 - 4 self |
BibTeX
@INPROCEEDINGS{Jouppi93tradeoffsin,
author = {Norman P. Jouppi and Steven J. E. Wilton},
title = {Tradeoffs in Two-Level On-Chip Caching},
booktitle = {In Proceedings of the 21st Annual International Symposium on Computer Architecture},
year = {1993},
pages = {34--45}
}
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Abstract
The performance of two-level on-chip caching is investigated for a range of technology and architecture assumptions. The area and access time of each level of cache is modeled in detail. The results indicate that for most workloads, twolevel cache configurations (with a set-associative second level) perform marginally better than single-level cache configurations that require the same chip area once the first-level cache sizes are 64KB or larger. Two-level configurations become even more important in systems with no off-chip cache and in systems in which the memory cells in the first-level caches are multiported and hence larger than those in the second-level cache. Finally, a new replacement policy called two-level exclusive caching is introduced. Two-level exclusive caching improves the performance of two-level caching organizations by increasing the effective associativity and capacity. d i g i t a l Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA...
Keyphrases
two-level on-chip caching two-level exclusive caching set-associative second level memory cell off-chip cache western research laboratory single-level cache configuration twolevel cache configuration new replacement policy university avenue palo alto architecture assumption two-level caching organization chip area second-level cache first-level cache size two-level configuration effective associativity first-level cache access time
