Abstract

This paper describes the architectural and organizational tradeoffs made during the design of the MultiTitan, and provides data supporting the decisions made. These decisions covered the entire space of processor design, from the instruction set and virtual memory architecture through the pipeline and organization of the machine. In particular, some of the tradeoffs involved the use of an on-chip instruction cache with off-chip TLB and floating-point unit, the use of direct-mapped instead of associative caches, the use of a 64-bit vs. 32-bit data bus, and the implementation of hardware pipeline interlocks. This is a preprint of a paper that will be presented at the 16th Annual International Symposium on Computer Architecture, IEEE and ACM, Jerusalem, Israel, May 28-June 1, 1989. An early draft of this paper appeared as WRL Technical Note TN-8. Copyright 1989 ACM i 1. Introduction The MultiTitan is a high-performance general-purpose 32-bit microprocessor developed at Digital Eq...

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