Layout aware design of mesh based NoC architectures

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Layout aware design of mesh based NoC architectures

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by Krishnan Srinivasan , Karam S. Chatha

Venue:	in Proceedings of the 4th international conference on Hardware/software codesign and system synthesis. ACM
Citations:	7 - 0 self

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@INPROCEEDINGS{Srinivasan_layoutaware,
    author = {Krishnan Srinivasan and Karam S. Chatha},
    title = {Layout aware design of mesh based NoC architectures},
    booktitle = {in Proceedings of the 4th international conference on Hardware/software codesign and system synthesis. ACM},
    year = {},
    pages = {141}
}

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Abstract

Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology such that power consumption is minimized, and performance constraints are satisfied. Technology scaling increases the contribution of the link power to the overall power consumption of the NoC. Since link power consumption is dependent on the length of the link, its contribution cannot be accurately estimated without system-level floorplanning. In this paper, we propose a novel design technique that integrates systemlevel floorplanning into the NoC design flow. Our technique invokes an existing floorplanner to generate an initial layout of the cores. This is followed by invocation of a novel low complexity algorithm that generates the mesh based NoC

Keyphrases

noc architecture layout aware design performance constraint link power consumption overall power consumption novel design technique novel low complexity algorithm regular mesh system-level floorplanning power consumption link power initial layout noc design flow contribution cannot traffic trace

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