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VLSI Implementation of Karatsuba Algorithm and Its Evaluation
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BibTeX
@MISC{Yazaki_vlsiimplementation,
author = {Syunji Yazaki and Kôki Abe},
title = {VLSI Implementation of Karatsuba Algorithm and Its Evaluation},
year = {}
}
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Abstract
VLSI implementation of Karatsuba algorithm for multi-digit multiplication was investigated. We designed 32-bit recursive Karatsuba multiplier (RKM) and found that its critical path delay and area cost are 9.44ns and 0.228mm 2, respectively. Next we designed and evaluated RKM of larger bits. For bit length less than 2 9, Wallace tree multiplier (WTM) has less area cost than RKM, while RKM has less area cost than WTM for bit length larger than 2 9. The area cost of multiplier of 2 9 bits is approximately 30mm 2. Critical path delay of RKM is always larger than that of WTM. We should use WTM instead of RKM as combinational circuits for iterative Karatsuba multiplier (IKM) to have better cost performance. keywords:multi-digit multiplier, Karatsuba, VLSI 1
