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Placement-Driven Technology Mapping for LUT-Based FPGAs (2003)
| Venue: | In Proceedings of the ACM Int. Syposium on FPGAs |
| Citations: | 17 - 1 self |
BibTeX
@INPROCEEDINGS{Lin03placement-driventechnology,
author = {Joey Y. Lin and Ashok Jagannathan and Jason Cong},
title = {Placement-Driven Technology Mapping for LUT-Based FPGAs},
booktitle = {In Proceedings of the ACM Int. Syposium on FPGAs},
year = {2003},
pages = {121--126}
}
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Abstract
In this paper, we study the problem of placement-driven technology mapping for table-lookup based FPGA architectures to optimize circuit performance. Early work on technology mapping for FPGAs such as Chortle-d[14] and Flowmap[3] aim to optimize the depth of the mapped solution without consideration of interconnect delay. Later works such as Flowmap-d[7], Bias-Clus[4] and EdgeMap consider interconnect delays during mapping, but do not take into consideration the effects of their mapping solution on the final placement. Our work focuses on the interaction between the mapping and placement stages. First, the interconnect delay information is estimated from the placement, and used during the labeling process. A placement-based mapping solution which considers both global cell congestion and local cell congestion is then developed. Finally, a legalization step and detailed placement is performed to realize the design. We have implemented our algorithm in a LUT based FPGA technology mapping package named PDM (Placement-Driven Mapping) and tested the implementation on a set of MCNC benchmarks. We use the tool VPR[1][2] for placement and routing of the mapped netlist. Experimental results show the longest path delay on a set of large MCNC benchmarks decreased by 12.3 % on the average.
Keyphrases
lut-based fpgas placement-driven technology mapping interconnect delay local cell congestion placement-driven technology large mcnc benchmark mapped netlist placement stage fpga architecture path delay early work mapped solution circuit performance interconnect delay information final placement tool vpr placement-based mapping solution technology mapping mapping solution mcnc benchmark legalization step placement-driven mapping detailed placement labeling process experimental result global cell congestion fpga technology
