Software Prefetching and Caching for Translation Lookaside Buffers

DMCA

Software Prefetching and Caching for Translation Lookaside Buffers (1994)

Cached

Download Links

Other Repositories/Bibliography

DBLP

by Kavita Bala , M. Frans Kaashoek , William E. Weihl

Citations:

52 - 4 self

BibTeX

@MISC{Bala94softwareprefetching,
    author = {Kavita Bala and M. Frans Kaashoek and William E. Weihl},
    title = {Software Prefetching and Caching for Translation Lookaside Buffers},
    year = {1994}
}

OpenURL

Abstract

A number of interacting trends in operating system structure, processor architecture, and memory systems are increasing both the rate of translation lookaside buffer (TLB) misses and the cost of servicing a miss. This paper presents two novel software schemes, implemented under Mach 3.0, to decrease both the number and the cost of kernel TLB misses (i.e., misses on kernel data structures, including user page tables). The first scheme is a new use of prefetching for TLB entries on the IPC path, and the second scheme is a new use of software caching of TLB entries for hierarchical page table organizations. For a range of applications, prefetching decreases the number of kernel TLB misses by 40% to 50%, and caching decreases TLB penalties by providing a fast path for over 90% of the misses. Our caching scheme also decreases the number of nested TLB traps due to the page table hierarchy, reducing the number of kernel TLB miss traps for applications by 20% to 40%. Prefetching and caching, ...

Keyphrases

translation lookaside buffer software prefetching tlb entry kernel tlb new use ipc path kernel tlb miss memory system decrease tlb penalty user page table software caching novel software scheme nested tlb trap operating system structure kernel data structure page table hierarchy hierarchical page table organization fast path processor architecture second scheme first scheme

DMCA