Abstract

In this paper, we study a hardware-supported, compiler-directed (HSCD) cache coherence scheme which relies mostly on compiler analysis, but which also needs a reasonable amount of hardware support. Such a scheme can be implemented on a large-scale multiprocessor using off-the-shelf microprocessors such as the Cray T3D, and can be adapted to various cache organizations including multi-word cache lines and byte-addressable architectures. Several system related issues, including critical sections, threads with inter-thread communication, and task migration have also been addressed. The cost of the required hardware support is small and proportional to the cache size. The necessary compiler algorithms, including intra- and interprocedural array data flow analysis, have been implemented on the Polaris paralleling compiler [31]. From our simulation study using the Perfect Club benchmarks [5], we found that in spite of conservative decisions made by the compiler, the performance of the propos...

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