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Optimizing Heterogeneous NoC Design
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@MISC{Ben-itzhak_optimizingheterogeneous,
author = {Yaniv Ben-itzhak and Israel Cidon and Avinoam Kolodny},
title = {Optimizing Heterogeneous NoC Design},
year = {}
}
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Abstract
We develop a novel design methodology that optimizes capacity of each link in a NoC and the numbers of virtual channels (VCs) at each router port for a given set of flows and latency constraints. In order to lower computation costs associated with a simulated annealing search in the design space, we utilize an approximate analysis of the NoC performance thus replacing the need for a NoC simulation. Therefore, computation time and resources are dramatically reduced. The area saving achieved by our heterogeneous NoC design is demonstrated by several use-cases. The heterogeneous NoC design process is applied to SoCs running multimedia benchmarks, and to Chip-Multi-Processor (CMP) running PARSEC benchmark programs. Categories and Subject Descriptors
Keyphrases
heterogeneous noc design noc performance parsec benchmark program computation cost novel design methodology router port latency constraint several use-cases subject descriptor heterogeneous noc design process virtual channel noc simulation design space approximate analysis computation time simulated annealing search
