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Fast Construction of SAH BVHs on the Intel Many Integrated Core (MIC) Architecture
| Venue: | IEEE Transactions on Visualization and Computer Graphics |
| Citations: | 7 - 0 self |
BibTeX
@ARTICLE{Wald_fastconstruction,
author = {Ingo Wald},
title = {Fast Construction of SAH BVHs on the Intel Many Integrated Core (MIC) Architecture},
journal = {IEEE Transactions on Visualization and Computer Graphics},
year = {}
}
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Abstract
Abstract — We investigate how to efficiently build bounding volume hierarchies (BVHs) with surface area heuristic (SAH) on the Intel Many Integrated Core (MIC) Architecture. To achieve maximum performance, we use four key concepts: progressive 10-bit quantization to reduce cache footprint with negligible loss in BVH quality; an AoSoA data layout that allows efficient streaming and SIMD processing; high-performance SIMD kernels for binning and partitioning; and a parallelization framework with several build-specific optimizations. The resulting system is more than an order of magnitude faster than today’s high-end GPU builders for comparable BVHs; it is usually faster even than spatial median builders; it can build SAH BVHs almost as fast as existing GPUs and CPUs- and CPU-based approaches can build regular grids; and in aggregate “build+render ” performance is significantly faster than the best published numbers for either of these systems, be it CPU or GPU, BVH, kd-tree, or grid.
Keyphrases
intel many integrated core sah bvhs fast construction surface area bvh quality today high-end gpu builder maximum performance aosoa data layout published number several build-specific optimization spatial median builder parallelization framework volume hierarchy progressive 10-bit quantization simd processing aggregate build render performance negligible loss comparable bvhs regular grid key concept cache footprint cpu-based approach high-performance simd kernel
