A Cascade Realization of Multiple-Output Function for Reconfigurable Hardware (2001)
| Venue: | INTERNATIONAL WORKSHOP ON LOGIC AND SYNTHESIS (IWLS01), LAKE TAHOE, CA |
| Citations: | 28 - 24 self |
BibTeX
@INPROCEEDINGS{Sasao01acascade,
author = {Tsutomu Sasao and Munehiro Matsuura and Yukihiro Iguchi},
title = {A Cascade Realization of Multiple-Output Function for Reconfigurable Hardware},
booktitle = {INTERNATIONAL WORKSHOP ON LOGIC AND SYNTHESIS (IWLS01), LAKE TAHOE, CA},
year = {2001},
pages = {12--15},
publisher = {}
}
Bookmark
 |
 |
 |
 |
 |
 |
OpenURL
Abstract
A realization of multiple-output logic functions using a RAM and a sequencer is presented. First, a multiple-output function is represented by an encoded characteristic function for non-zeros (ECFN). Then, it is represented by a cascade of look-up tables (LUTs). And finally, the cascade is simulated by a RAM and a sequencer. Multiple-output functions for benchmark functions are realized by cascades of LUTs, and the number of LUTs and levels of cascades are shown. A partition method of outputs for parallel evaluation is also presented. A prototype has been developed by using RAM and FPGA.
